1. Field of the Invention
The present invention relates to a data processing apparatus including a CPU (Central Processor Unit).
2. Description of the Related Art
In general, a CPU incorporated in a data processing machine reads and executes commands and instructions from a memory in response to a pulse signal produced periodically (i.e., clock signal). A frequency of the clock signal governs the fundamental operation of the data processing machine so that the clock signal frequency must be maintained appropriately. A crystal oscillator is, for example, used to maintain the clock signal frequency.
In recent years, small, lightweight data processing devices (e.g., cellular phones and PDA (Personal Data Assistant) devices) are used by many people. The small, lightweight data processing device should have a high throughput speed and should not consume battery electricity quickly. Usually, the small, lightweight data processing device is a portable electronic device. If a battery runs out, the portable data processing device does not work. The CPU is an element which consumes electricity most. One approach to reduce the electric power consumption by the CPU is to temporarily decrease the clock frequency for the CPU.
Japanese Patent Application Kokai No. 61-286913 teaches a method of adjusting a clock frequency of an electronic device having a CPU, in accordance with a hardware signal. Japanese Patent Application Kokai No. 61-286913 discloses one embodiment, in which the hardware signal is input in response to connection (or disconnection) of an AC adapter, and the clock frequency of the CPU is varied with the inputting of the hardware signal. In Japanese Patent Application Kokai No. 61-286913, however, the CPU-cannot recognize the change of the clock frequency. Thus, a memory access timing is not adjusted appropriately when the clock frequency is adjusted. This is because a memory access time includes a certain period to finish an address decoding process and other related processes. Before the CPU really becomes ready to retrieve data from a memory, a wait time which is worth of several clocks should be inserted into the memory access time. If the clock frequency dynamically changes, the wait time must be changed correspondingly in order to avoid an access error. In general, the wait time is expressed by the number of clocks needed. For example, one wait time (or wait time number “1”) is a waiting period of one clock long.
In order to overcome such drawbacks of Japanese Patent Application Kokai No. 61-286913, Japanese Patent Application Kokai No. 9-319651 proposed an approach applicable to a single-chip microcomputer having a memory. When a clock frequency changes, the wait time to the memory access is also changed by software control. This eliminates the problem of the adjustment of the memory access wait time. However, since the software adjusts the memory access wait time, the software (or the microcomputer) suffers from overhead and consumes a relatively large amount of electricity. Further, the following problem arises due to time discrepancy between when the clock frequency changes and when the memory access wait time changes.
If the clock is fast, a long memory access wait time should be inserted (the faster, the longer). If the clock is slow, a short wait time should be inserted. Therefore, if the memory access wait time is shortened while the clock speed is still high during the process of changing the fast clock (i.e., high frequency clock) to the slow clock (i.e., low frequency clock), the access is missed. In order to avoid this, the memory access wait time should be shortened after the clock speed has dropped. In this case, however, the clock is slow whereas a long wait time is included for a certain period.
Likewise, the low speed clock should be changed to the high speed clock after the wait time is increased to match the high speed clock. This creates a situation in which the clock is slow whereas the long wait time is set during the transition period from the low speed clock to the high speed clock. As a result, the memory access cannot be performed in an originally designed way during the transition period.
In addition, Japanese Patent Application Kokai No. 9-319651 was developed on the assumption that there is only one clock change request. In other words, Japanese Patent Application Kokai No. 9-319651 cannot deal with a case where there are a plurality of clock change requests. Consequently, it is not possible to perform delicate processing in response to various types of clock change requests.